This invention relates generally to integrated circuits and in particular to a memory address decode array with vertical transistors.
Modern electronic systems typically include a data storage device such as a dynamic random access memory (DRAM), static random access memory (SRAM), video random access memory (VRAM), erasable programmable read only memory (EPROM), flash memory, or other conventional memory device. As these systems become more sophisticated, they require more and more memory in order to keep pace with the increasing complexity of software based applications that run on the systems. Thus, as the technology relating to memory devices has evolved, designers have tried to increase the density of the components of the memory device. For example, the electronics industry strives to decrease the size of memory cells that store the data in the memory device. This allows a larger number of memory cells to be fabricated without substantially increasing the size of the semiconductor wafer used to fabricate the memory device.
Memory devices store data in vast arrays of memory cells. Essentially, the cells are located at intersections of wordlines and bitlines (rows and columns of an array). Each cell conventionally stores a single bit of data as a logical xe2x80x9c1xe2x80x9d or a logical xe2x80x9c0xe2x80x9d and can be individually accessed or addressed. Conventionally, each cell is addressed using two multi-bit numbers. The first multi-bit number, or row address, identifies the row of the memory array in which the memory cell is located. The second multi-bit number, or column address, identifies the column of the memory array in which the desired memory cell is located. Each row address/column address combination corresponds to a single memory cell.
To access an individual memory cell, the row and column addresses are applied to inputs of row and column decoders, respectively. Conventionally, row and column decoders are fabricated using programmable logic arrays. These arrays are configured so as to select desired word and bit lines based on address signals applied to the inputs of the array. As with the array of memory cells, the decoder arrays use a portion of the surface area of the semiconductor wafer. Thus, designers also strive to reduce the surface area required for the decoder arrays.
Memory devices are fabricated using photolithographic techniques that allow semiconductor and other materials to be manipulated to form integrated circuits as is known in the art. These photolithographic techniques essentially use light that is focussed through lenses and masks to define patterns in the materials with microscopic dimensions. The equipment and techniques that are used to implement this photolithography provide a limit for the size of the circuits that can be formed with the materials. Essentially, at some point, the lithography cannot create a fine enough image with sufficient clarity to decrease the size of the elements of the circuit. In other words, there is a minimum dimension that can be achieved through conventional photolithography. This minimum dimension is referred to as the xe2x80x9ccritical dimensionxe2x80x9d (CD) or minimum xe2x80x9cfeature sizexe2x80x9d (F) of the photolithographic process. The minimum feature size imposes one constraint on the size of the components of a memory device, including the decoder array. In order to keep up with the demands for higher capacity memory devices, designers search for other ways to reduce the size of the components of the memory device, including the decoder array.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a decoder array that uses less surface area of a semiconductor wafer as compared to conventional decoder arrays.
The above mentioned problems with decoder arrays and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A circuit and method for a decoder array using vertical transistors is provided.
In particular, one embodiment of the present invention provides a decoder for a memory device. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. A number of vertical transistors are selectively disposed at intersections of output lines and address lines. Each transistor is formed in at least one pillar of semiconductor material that extends outwardly from a working surface of a substrate. The vertical transistors each include source, drain, and body regions. A gate is also formed along at least one side of the at least one pillar and is coupled to one of the number of address lines. The transistors in the array implement a logic function that selects an output line responsive to an address provided to the address lines.
In another embodiment, a memory device is provided. The memory device includes an array of word lines and complementary bit line pairs. A number of memory cells are each addressably coupled at intersections of a word line with a bit line of a complementary bit line pair. A row decoder is coupled to the word lines so as to implement a logic function that selects one of the word lines responsive to an address provided to the row decoder. A number of sense amplifiers are each coupled to a complementary pair of bit lines. A column decoder is coupled to the sense amplifiers so as to implement a logic function that selects one of the complementary pairs of bit lines responsive to an address provided to the column decoder. The row decoder comprises an array of vertical transistors that are selectively coupled to implement a logic function that selects a wordline based on a supplied address.
In another embodiment, a method of forming a logic array for a decoder is provided. The method includes forming an array of pillars of semiconductor material. Each pillar includes a first source/drain region, a body region and a second source/drain region that are vertically stacked and that extend outwardly from a substrate. A number of address lines are formed in trenches that separate rows of pillars. Selected pillars are gated with the address lines. Output lines are formed orthogonal to the address lines. The output lines each interconnect the second source/drain regions of pillars in a column of the array so as to implement a selected logic function.